The ongoing drive to miniaturize integrated circuits would be futile without the commensurate ability to image finer features onto prior patterns within proportionately smaller tolerances. Consequently, methods to improve alignment accuracy continue to be of primary importance both in the introduction of new and yield improvement of existing technologies.
Refining overlay measurements has been an important part of reducing overlay budgets because engineers can only improve what can be accurately measured. Measurability has been improved by refining hardware, edge detection and calibration algorithms predominately using visible light though other techniques have been studied. Many process layers such as shallow trench isolation (STI) and copper dual damascene require target optimization to improve readability and/or reduce asymmetry in the printed targets.
Significant advances towards improving overlay have occurred because stepper manufacturers have continually improved stage movement reproducibility. In addition, current exposure tools provide the user with parameters, commonly called “correctables,” that can compensate stage movement, and lens and reticle placement to optimize alignment onto prior layers. Various steppers implement different, though usually related, sets of correctable offsets. Methods for modeling these parameters have become important to minimize misalignment across stepper fields and wafers.
In striving to optimize inter-layer alignment, each of the error-causing variables can be corrected by a different part of the stepper. If errors are not segregated and measured independently, then the error measurements are confounded and the resulting corrections for each variable may be contradictory and self-defeating. A number of parameters have to be accounted for in preparing the wafer stepper to print patterns on the substrates with minimal error. Refer to Table 1.
There are a number of techniques for improving alignment accuracy of particular wafer stepper parameters. In a prior art process, described in U.S. Pat. No. 6,258,611 B1 (issued Jul. 10, 2001), titled, “Method for Determining Translation Portion of Misalignment Error in a Stepper,” herein incorporated by reference in its entirety, there is a method for determining the translation portion (Rx0, Ry0) of misalignment error in a stepper. In an example embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer in the stepper. In another step a first pattern, including an error-free fine alignment target, is created on the wafer. Next, the wafer is realigned in the stepper using the error-free alignment target. Then a second pattern is created on the wafer overlaying the first pattern. In another step, the translation error between the first pattern and second pattern is measured.
In another prior art process, described in U.S. patent application Ser. No. 09/422,909 (filed on Oct. 21, 1999) titled, “Method for Determining Rotational Error Portion of Total Misalignment Error in a Stepper,” herein incorporated by reference in its entirety, there is a method for determining the rotational error portion of (RChipRot, RxWafRot, RyWafRot) total misalignment error in a stepper. In an example embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer, having a first pattern and an error-free fine alignment target, in the stepper. In another step, the wafer is aligned in the stepper using the error-free alignment target. A second pattern is created on the wafer overlaying the first pattern. In another step, the rotational error portion of the total misalignment error is determined by measuring the circumferential misalignment between the first pattern and the second pattern.
In yet another prior art process, described in U.S. patent application Ser. No. 09/422,914 (filed on Oct. 21, 1999) titled, “Method for Determining Magnification Error Portion of Total Misalignment Error in a Stepper,” herein incorporated by reference in it entirety, there is a method for determining he magnification error portion (RChipMag, RxWafMag, RyWafMag) of total misalignment error in a stepper. In an example embodiment, the method comprise a series of steps in a stepper, starting with the step of receiving a wafer, having a first pattern and an error-free alignment target, in the stepper. In another step, the wafer is aligned in the stepper using the error-free fine alignment target. A second pattern is created on the wafer overlaying the first pattern. In another step, the magnification error portion of the total misalignment error is determined by measuring the radial misalignment between the first pattern and the second pattern.
In any of the three processes described above, distortion-free calibration wafers are prepared. In an example process, wafers, upon which photo resist is applied, are loaded into a stepper. The stepper is adjusted to reduce scaling and orthogonality on bare silicon wafers to less than 0.1 ppm. The center die (5.247 mm×5.247 mm) of a 5×5 chip test reticle is stepped across the entire wafer by adjusting the aperture blades. This center die is projected by the center location of the stepper lens. The lens center has minimal distortion. This stepping distance is chosen since 5×5 die match the same reticle opened to full field and stepped at 26.35 mm×26.235 mm increments. The wafers are developed and the patterns are lightly etched into the silicon. The calibration wafers have a first layer pattern that is free of lens distortions. Each sub-field has contains the required marks to align a second layer pattern to it. Refer to FIG. 1A
Having made the calibration wafers with an error-free first layer, a second layer, as shown in FIG. 1B, is printed on the calibration wafer as a full shot, the entire reticle plate projected through the full aperture of the stepper lens. The errors may be calculated from the positions of the artifacts printed on the second layer relative to the positions of the distortion-free artifacts printed and etched onto the first layer.
The above method enables one to measure components of alignment when aligning to a perfect grid. There exists a need for structures that have calibrated offsets from perfect grids so that responses to misalignment can be measured.